1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and a manufacturing method thereof, and particularly to the semiconductor integrated circuit device having a self-aligned contact structure and the manufacturing method thereof.
2. Related Art
Miniaturization of wirings has been progressed in order to improve characteristics and yield of semiconductor integrated circuit devices. In a manufacture process of the miniaturized semiconductor integrated circuit device, the problem arises that a design size of a contact hole (=hole diameter+design margin) becomes too large when the design margin of the contact hole is determined in consideration of variation in alignment with an under layer wiring. The variation in the alignment results from insufficient alignment performance of a reduction projection exposure apparatus used in the photolithography. Moreover, the variation is particularly difficult to be scaled down among various scaling factors involved in a semiconductor process, and is even said to affect determination on limitation of the exposure technology more than resolution.
For this reason, a self-aligned contact (SAC) process has been used principally in recent years wherein the design margin for the alignment can be made unnecessary on a photomask.
Hereinbelow, the SAC process using a nitride film sidewall as an etching stopper is described by reference to the drawings. FIG. 7 is a schematic cross sectional view of steps illustrating the SAC process disclosed in Japanese Patent Laid-Open No. 9-050986 (Patent Document 1).
In the SAC process of FIG. 7, a gate insulation film 102 is formed on the surface of a silicon substrate 101, and then gate electrodes 103 are formed thereon. Here, the gate electrode 103 is constituted of tungsten polycide. On the gate electrode 103, offset oxide films 104 are formed. Then, first sidewall insulation films 105 are formed on both sides of each gate electrode 103 and offset oxide film 104. Here, the offset oxide film 104 and the first sidewall insulation film 105 are constituted of an SiOx film (here, the SiOx film is a silicon oxide film).
Subsequently, source/drain diffusion layers 106 with an LDD structure are formed, followed by stacking an SiN etching stopper film 107 and an interlayer insulation film 108 thereon. The SiN etching stopper film 107 is a silicon nitride film of approximately 50 nm in thickness formed by the Low Pressure Chemical Vapor Deposition (LP-CVD) method. The interlayer insulation film 108 is the SiOx film.
Next, a resist mask 109 is formed (FIG. 7(A)), and the interlayer insulation film 108 is selectively dry-etched by using the resist mask 109 to form a contact hole 110. Here, the SiN etching stopper film 107 serves as an etching stopper which protects the offset oxide film 104 and the first sidewall insulation film 105 from the dry etching (FIG. 7(B)).
Then, an etching gas for the dry etching is changed to selectively etch back the SiN etching stopper film 107, and a contact hole 110a which exposes the surface of the silicon substrate 101 is formed. On the exposed surface of the contact hole 110a, the SiN etching stopper film 107 is etched back which partially remains on the side face of the first sidewall insulation film 105 to form a second sidewall insulation film 107a. A wiring 111 is formed which connects to the source/drain diffusion layer 106 via the contact hole 110a formed in this manner (FIG. 7(C)). Here, the wiring 111 is a publicly known stacked wiring.
As the semiconductor device becomes still more miniaturized, the SAC technique is used abundantly while the miniaturization of the SAC structure becomes indispensable. Particularly, in the case of a Dynamic Random Access Memory (DRAM) where the contact hole is formed by the SAC process which connects a diffusion layer of a memory cell section constituted of one capacitor and one MOS transistor with a bit line, the SAC structure must be miniaturized even further.
Next, the miniaturization of the above described SAC structure is described. FIG. 8 is a schematic cross sectional view in the order of manufacturing steps of the SAC disclosed in Japanese Patent Laid-Open No. 2002-319551 (Patent Document 2).
As illustrated in FIG. 8(A), gate insulation films 202 and 202a are formed on the surface of a silicon substrate 201, and then gate electrodes 203 and 203a are formed thereon, respectively. Here, the gate electrodes 203 and 203a have a polycide structure such as a WSi layer/a polycrystalline silicon layer. On the gate electrodes 203 and 203a, protective insulation films 204 and 204a are formed. Here, the protective insulation films 204 and 204a are silicon nitride films. Then, source/drain diffusion layers 205 and 205a are formed.
Subsequently, as illustrated in FIG. 8(B), a blanket insulation film 206 is formed on the whole surface. The blanket insulation film 206 is a silicon nitride film with approximately 30 nm in thickness, depositing on the surfaces of the gate electrodes 203 and 203a, the protective insulation films 204 and 204a, and the source/drain diffusion layers 205 and 205a. Here, the major difference with the case of FIG. 7 is that there is no sidewall insulation film on the side face of the gate electrode or the like.
Next, an interlayer insulation film 207 is stacked on the blanket insulation film 206. Here, the interlayer insulation film 207 is a silicon oxide film planarized by the Chemical Mechanical Polishing (CMP) method.
Next, although not illustrated, a resist mask is provided, which is used as the etching mask to dry-etch the interlayer insulation film 207. The dry etching in this case is performed by Reactive Ion Etching (RIE) apparatus which uses two radio frequencies (RF). Here, plasma excitation of an etching gas is carried out by the RF of 13.56 MHz to 60 MHz. The RF of around 1 MHz is then added. In this conventional art, nitrogen (N2) is added to a mixed gas of C5F8 and O2 as the etching gas in such 2 RF RIE. An argon (Ar) gas is then added to the mixed gas to carry out the plasma excitation. With such an etching gas, the etch rate of the protective insulation layers 204 and 204a or the blanket insulation film 206 under the interlayer insulation film 207 is reduced substantially. In other words, the ratio of the etch rate of the silicon nitride film (Si3N4) to the etch rate of the silicon oxide (SiO2) film can be reduced under a high controllability. Thus, the etching of the blanket insulation film 206 or the protective insulation layers 204 and 204a would hardly take place at the RIE step of the interlayer insulation film 207.
Subsequently, the etching gas is changed to the mixed gas of CHF3 and CO to perform the 2 RF RIE, so that the blanket insulation film 206 on the bottom is removed to expose the surface of the diffusion layer 205. In this manner, the blanket insulation film 206a is left on the sidewalls of the gate electrodes 203 and 203a and the protective insulation layers 204 and 204a as illustrated in FIG. 8(C). Here, the film thickness of the remaining blanket insulation film 206a is approximately 25 nm. Thus, as illustrated in FIG. 8(C), a contact hole 208 is formed which reaches the surface of the diffusion layer 205.
Thereafter, although not illustrated, a contact plug is formed in the above described contact hole 208, and the bit line connected to the contact plug is allocated thereon.
As the miniaturization of the contact hole progresses with the above described technique and thus resistance of the contact plug increases, it is concerned that a signal transmission rate would become slow. As what improves this point, a landing plug contact is disclosed in Japanese Patent Laid-Open No. 2003-338542 (Patent Document 3) which is a kind of the SAC process of forming plug polysilicon in portions of a bit line contact and of a charge storage electrode contact after forming a word line.
Hereinbelow, the method of forming the contact plug disclosed in Japanese Patent Laid-Open No. 2003-338542 is described by reference to FIG. 9. The steps through forming the contact hole are similar to those of the conventional art.
As illustrated in FIG. 9(A), on a substrate 300, a transistor provided with a gate insulation film 301, a gate electrode 302, and a source/drain junction 305 is formed, and an interlayer insulation film 306 is then formed. A capping insulation film 303 is formed over the gate electrode 302, while a spacer insulation film 304 is formed at the side thereof.
The spacer insulation film 304 is formed at the side of the gate electrode by forming the silicon nitride film or the like on the semiconductor substrate comprising the gate electrode 302 and by performing etch-back the whole surface. In this case, however, upon etching back the whole surface for forming the spacer, over-etching of approximately 30% is performed preferably so as to ensure that the surface of the semiconductor substrate 300 is exposed.
The gate electrode 302 has also a typical structure constituted with a conductive body made with a polysilicon layer or stacked polysilicon layers, a diffusion barrier and so forth. Moreover, various types of the oxide films are used for the interlayer insulation film 306, e.g., boro phospho silicate glass (BPSG), spin on glass (SOG), undoped silicate glass (USG), phospho silicate glass (PSG) and so on. After forming the interlayer insulation film 306 in this manner, a CMP process or a flow process to the interlayer insulation film 306 is performed to planarize a surface of the inter-layer insulating layer 306.
Next, a landing plug contact hole is formed by performing the etching step utilizing a contact mask (not illustrated) and a native oxidation film formed in the contact hole is removed through the washing step. For the etching process for forming the contact hole, the etching is overly carried out exceeding in approximately 30% more than a regular etching to form firmly the contact hole so as to expose the substrate 300.
After the etching step for forming the contact hole, the washing step for removing the native oxidation film is performed in the method disclosed in this conventional art in which an in situ washing step such as hydrogen baking or a rapid heat treatment is not performed but only the general washing step is performed. In other words, the natural oxidation film inside the contact hole is removed by the general washing step utilizing a BOE (Buffered Oxide Etchant), an HF (Hydrogen Fluoride) solution, or an HF gas. A wafer with which the etching step and the washing step are performed as described above moves into a high vacuum system for being used in the following step. In this case, if the wafer is set so as to move into the high vacuum system within approximately two hours after the washing step, growth of the native oxidation film would be negligible.
Next, as illustrated in FIG. 9(B), single crystal silicon 308 is grown epitaxially on the bottom of the contact hole using the high vacuum system. While the single crystal silicon 308 is grown epitaxially on the bottom of the contact hole because it is the portion to contact with the silicon substrate 300, polysilicon 309, not the single crystal silicon, is formed at the sidewall portion of the contact hole because the portion contacts with the spacer insulation film 304 constituted of the nitride film or the like and the interlayer insulation film 306 constituted of the oxide film or the like.
The reason for using the high vacuum system is that it restrains growth of the native oxidation film and the single crystal silicon is readily grown epitaxially in the state with few impurities when the environment in a reaction chamber is high vacuum. In the method disclosed in this conventional art, the high vacuum state is utilized where the pressure in the reaction chamber is approximately 10−7 Pa to 10−4 Pa (10−9 to 10−6 Torr).
The epitaxially grown single crystal silicon 308 is grown epitaxially using the gas comprising Si, such as monosilane (SiH4) or disilane (Si2H6), as a source gas at a temperature of 550 to 800° C. so as to have the thickness of 5 to 20 nm from the bottom of the contact hole 307. The epitaxially grown single crystal silicon 308 may be used while undoped, or it may be doped with impurities such as phosphate (P) using a PH3 gas diluted with an inert gas such as He, N2, or Ar as a dopant gas.
The single crystal silicon 308 is grown epitaxially on the bottom of the contact hole 307 which contacts with the semiconductor substrate 300, while, at the sidewall of the contact hole, polysilicon 309 is formed with a predetermined thickness and then a polysilicon film 310 is deposited using a conventional batch type device, as illustrated in FIG. 9(C), to embed the contact hole 307. In depositing the polysilicon film 310 utilizing the conventional batch type device, the polysilicon film having the thickness of 150 to 300 nm is formed using the gas comprising silicon as the source gas at the temperature of 480 to 620° C. and a pressure of 26.7 to 200 Pa (0.2 to 1.5 Torr).
Thereafter, in order to reduce the resistance of a polysilicon plug, a subsequent doping step is performed wherein the PH3 gas diluted with the inert gas, such as He, N2, or Ar, is used as the dopant gas so that phosphorus (P) concentration may be set to 1.0×1020 to 3.0×1020 atoms/cm3. In this manner, the polysilicon film 310 is deposited over a whole structure comprising an upper portion of the interlayer insulation film 306 and an inner portion of the contact hole, followed by performing the CMP or etching back the whole surface until the surface of the interlayer insulation film 306 is exposed, to complete a contact plug 311 as illustrated in FIG. 9(D). When performing the CMP, slurry such as silica, alumina, or ceria with a particle size of 50 to 300 nm is used at pH 6 to 11.
However, in the SAC process disclosed in these conventional arts, there is the problem that a gate threshold voltage varies because hot electrons generated at the end of the gate electrode are trapped at the interface of the silicon nitride film due to the presence of the silicon nitride film at the end of the gate electrode. In order to avoid this problem, the technique is disclosed in Japanese Patent Laid-Open No. 11-307759 (Patent Document 4) which uses an LDD sidewall stacked of a TEOS-NSG film and the silicon nitride film.
Hereinbelow, an LDD sidewall formation method disclosed in Japanese Patent Laid-Open No. 11-307759 is described by reference to FIG. 10.
A gate oxide film 402a is formed on a silicon substrate 401 at 4 nm in thickness by the thermal oxidation, and subsequently gate polysilicon 403a is deposited thereon at 150 nm in thickness by the CVD.
The gate oxide film 402a and the gate polysilicon 403a are patterned in the form of the gate electrode by the lithography and dry etching, as illustrated in FIG. 10(B), to form a gate insulation film 402 and a gate electrode 403, respectively.
Then, as illustrated in FIG. 10(C), arsenic ions (As+) are implanted in the surface of the silicon substrate 401 using the gate electrode 403 as a mask under the condition of a dose amount of 2.5×1013 cm−2 and an implantation energy of 30 keV to form a shallow impurities implantation region 404.
As illustrated in FIG. 10(D), tetraethyl orthosilicate (TEOS) is supplied on the substrate surface at 300 sccm by the LP-CVD method to form a TEOS-NSG (non-doped silicate glass) film 405 at 10 to 20 nm in thickness under the condition of a degree of vacuum of 133 Pa (1 Torr) and a substrate temperature of 600 to 700° C. Then, dichlorosilane (SiH2Cl2) and ammonia (NH3) are supplied at 60 sccm and 600 sccm, respectively, using the LP-CVD method to form a silicon nitride film 406 at 80 to 90 nm in thickness under the condition of the degree of vacuum of 33.3 Pa (0.25 Torr) and the temperature of 700 to 800° C.
A stacked structure of the TEOS-NSG film 405 and the silicon nitride film 406 is dry-etched to form a sidewall insulation film 407 with a two-layer structure of the TEOS-NSG film 405 and the silicon nitride film 406 as illustrated in FIG. 10(E).
Next, as illustrated in FIG. 10(F), the arsenic ions (As+) are implanted into a deep region of the substrate surface using the gate electrode 403 and the sidewall insulation film 407 as the mask under the condition of the dose amount of 2.5×1015 cm−2 and the implantation energy of 50 keV and then thermal annealing is performed to form a source/drain region 408 with the LDD structure.
Subsequently, a titanium film is formed on the substrate surface and unreacted titanium is removed after a heat treatment to form a titanium silicide layer 409 on the surface of the source/drain region 408 and the surface of the gate electrode 403.
In the SAC process disclosed in Patent Documents 1 to 3, it is required to use the silicon nitride film which serves as the etching stopper to form the contact hole. For this reason, the gate threshold voltage may vary because the silicon nitride film is present between the gate electrode and the contact plug resulting in the silicon nitride film being adjacent to the semiconductor substrate so that electrons of a channel formed on the surface of the semiconductor substrate are trapped under the sidewall of the silicon nitride film.
In addition, where the LDD sidewall is the stacked structure as in Patent Document 4, the contact hole has to be formed while the sidewall has been formed. Consequently, in a DRAM semiconductor memory, a space between the gates becomes narrow while a planar area allowed for the contact hole decreases as the miniaturization progressing, resulting in the dry etching processing being very difficult. Moreover, in the DRAM process, it is required to form the silicon nitride film for substrate antioxidation between the contacts, leading to the problem that the space between the contacts further becomes narrower disabling to respond to the miniaturization.